CPU 速通系列 2-3：ID-EX 模块

 1`include "defines.svh"
 2
 3module id_ex (
 4
 5    input logic clk,
 6    input logic rst,
 7
 8    //来自控制模块的信息
 9    input logic [5:0] stall,
10
11    //从译码阶段传递的信息
12    input logic [  `AluOpBus] id_aluop,
13    input logic [ `AluSelBus] id_alusel,
14    input logic [    `RegBus] id_reg1,
15    input logic [    `RegBus] id_reg2,
16    input logic [`RegAddrBus] id_wd,
17    input logic               id_wreg,
18    input logic [    `RegBus] id_link_address,
19    input logic               id_is_in_delayslot,
20    input logic               next_inst_in_delayslot_i,
21
22    //传递到执行阶段的信息
23    output logic [  `AluOpBus] ex_aluop,
24    output logic [ `AluSelBus] ex_alusel,
25    output logic [    `RegBus] ex_reg1,
26    output logic [    `RegBus] ex_reg2,
27    output logic [`RegAddrBus] ex_wd,
28    output logic               ex_wreg,
29    output logic [    `RegBus] ex_link_address,
30    output logic               ex_is_in_delayslot,
31    output logic               is_in_delayslot_o
32
33);
34
35    always_ff @(posedge clk) begin
36        if (rst == `RstEnable) begin
37            ex_aluop           <= `EXE_NOP_OP;
38            ex_alusel          <= `EXE_RES_NOP;
39            ex_reg1            <= `ZeroWord;
40            ex_reg2            <= `ZeroWord;
41            ex_wd              <= `NOPRegAddr;
42            ex_wreg            <= `WriteDisable;
43            ex_link_address    <= `ZeroWord;
44            ex_is_in_delayslot <= `NotInDelaySlot;
45            is_in_delayslot_o  <= `NotInDelaySlot;
46        end else if (stall[2] == `Stop && stall[3] == `NoStop) begin
47            ex_aluop           <= `EXE_NOP_OP;
48            ex_alusel          <= `EXE_RES_NOP;
49            ex_reg1            <= `ZeroWord;
50            ex_reg2            <= `ZeroWord;
51            ex_wd              <= `NOPRegAddr;
52            ex_wreg            <= `WriteDisable;
53            ex_link_address    <= `ZeroWord;
54            ex_is_in_delayslot <= `NotInDelaySlot;
55        end else if (stall[2] == `NoStop) begin
56            ex_aluop           <= id_aluop;
57            ex_alusel          <= id_alusel;
58            ex_reg1            <= id_reg1;
59            ex_reg2            <= id_reg2;
60            ex_wd              <= id_wd;
61            ex_wreg            <= id_wreg;
62            ex_link_address    <= id_link_address;
63            ex_is_in_delayslot <= id_is_in_delayslot;
64            is_in_delayslot_o  <= next_inst_in_delayslot_i;
65        end
66    end
67
68endmodule